A structure of a conventional PLL frequency synthesizer is illustrated in FIG. 11.
The conventional PLL frequency synthesizer of FIG. 11 comprises a voltage control oscillator VCO, a programmable frequency divider DIV, a phase comparator PFD, a charge pump circuit CP, and a loop filter LF.
The voltage control oscillator VCO changes an oscillation frequency, depending on a potential of an oscillation frequency control signal VT (described below). The frequency divider DIV divides the oscillation frequency from the voltage control oscillator VCO with a frequency division ratio corresponding to an externally input channel selection signal. The phase comparator PFD detects a difference in phase between an output signal fDIV from the frequency divider DIV and an externally input reference signal fREF, and outputs a phase difference signal. The charge pump circuit CP causes a current to flow into or out of an output point, depending on the phase difference signal from the phase comparator PFD. The loop filter LF filters out a high frequency component of an output current from the charge pump circuit CP, and converts the output current into a direct current voltage value. An output of the loop filter LF is fed as the oscillation frequency control signal VT back to the voltage control oscillator VCO.
An output frequency fout of the thus-constructed conventional PLL frequency synthesizer is represented by a frequency represented by expression 1 below using a frequency fref of the reference signal and a division ratio N of the program frequency divider DIV.fout=N ·fref   (1)
In actual radio transmitter-receivers, a predetermined output frequency fout is obtained by changing the frequency fref of the reference signal or the frequency division ratio N, or both of them, and a signal of the output frequency fout is used as a local signal for transmission/reception of a radio signal.
An open loop gain GH(s) of the PLL frequency synthesizer is represented by expression 2 below.
                              GH          ⁡                      (            s            )                          =                              K            p                    ·                                    Z              lf                        ⁡                          (              s              )                                ·                                    K              VCO                        s                    ·                      1            N                                              (        2        )            
In expression 2, KVCO is a sensitivity of the voltage control oscillator VCO, N is a frequency division number, Zif(s) is a transfer function of a loop filter, Kp is a conversion gain of the phase comparator PFD and the charge pump circuit CP. The conversion gain Kp is represented by expression 3 below, where a charge pump current is indicated by ICP.
                              K          p                =                              I            CP                                2            ⁢            π                                              (        3        )            
The sensitivity KVCO of the voltage control oscillator VCO is represented by a proportion of a change in oscillation frequency with respect to a change in the input oscillation frequency control signal VT. In an LC-type voltage control oscillator LC-VCO which is generally used as a PLL frequency synthesizer of a wireless communications apparatus, the oscillation frequency control signal VT is output to a variable capacitor, and the capacitance value of the variable capacitor varies depending on a voltage of the oscillation frequency control signal VT, thereby changing an oscillation frequency of the voltage control oscillator VCO.
Here, the variable capacitance characteristics of a MOS-type variable capacitor which is frequently used as a variable capacitor or a p-n junction-type variable capacitor are generally nonlinear with respect to an input (i.e., the oscillation frequency control signal VT). As a result, the oscillation frequency characteristics of the voltage control oscillator VCO are also nonlinear with respect to the input oscillation frequency control signal VT. A general voltage control oscillator VCO which employs a j-n junction capacitor as a variable capacitor has characteristics of an oscillation frequency fVCO as illustrated in FIG. 12(a), and characteristics of the sensitivity KVCO as illustrated in FIG. 12(b). Here, the charge pump current ICP is a constant current as illustrated in FIG. 12(c). Therefore, the open loop gain GH(s) of the PLL frequency synthesizer having such a voltage control oscillator VCO is nonlinear as illustrated in FIG. 12(d), so that the loop gain characteristics of the whole PLL frequency synthesizer varies depending on the potential of the oscillation frequency control signal VT. The variation of the loop gain characteristics due to the potential of the oscillation frequency control signal VT is responsible for variation of a lock-up time, variation of phase noise characteristics, and the like, i.e., degradation of characteristics.
In order to solve the above-described problem, a conventional technique is proposed in Patent Document 1. In this technique, the oscillation frequency control signal VT is A/D converted, and a transient response in a convergence process of the PLL frequency synthesizer is detected by high-speed sampling using a DSP (Digital Signal Processor) to obtain the sensitivity KVCO of the voltage control oscillator VCO, and based on the result, the conversion gain Kp of the phase comparator PFD and the charge pump circuit CP is changed, thereby causing the transfer characteristics of the PLL frequency synthesizer to be constant.
Patent Document 1: Japanese Patent Unexamined Publication No. H10-154934